부산대학교 도서관

This paper introduces an optimal engineering procedure for qualifying a large package with coplanarity up to 16 mils, specifically addressing heterogeneous integration (HI) for high-performance computing and AI applications. The package dimensions can reach 120mm x 120mm with BGA pitches of 1.0mm or 0.92mm. The qualification process caters to HI technologies like Chiplet, CoWoS, AoA, and FOWLP. Key strategies include: a unique stencil design accounting for warpage, spacer blocks to prevent solder bridging, an SMT pallet design to counteract board warpage, and refined reflow profiles. Furthermore, edge bonding is implemented for enhanced thermal, shock, and vibration resilience. A comprehensive T0 validation, thermal cycling, and high-G shock testing validate package performance, ensuring it meets the stringent demands of advanced computing applications.