학술논문
A 3.96-4.84-GHz Dual-Path Charge Pump PLL Achieving 89.7-fsrms Integrated Jitter and −250.8-dB FOMPLL
Document Type
Periodical
Source
IEEE Transactions on Circuits and Systems II: Express Briefs IEEE Trans. Circuits Syst. II Circuits and Systems II: Express Briefs, IEEE Transactions on. 71(4):1909-1913 Apr, 2024
Subject
Language
ISSN
1549-7747
1558-3791
1558-3791
Abstract
This brief proposes a power-efficient sub-100-fs dual-path charge pump phase-locked loop (DPPLL). The noise contribution of the DPPLL is analyzed and an energy-efficient CP structure is proposed to achieve the improved in-band noise and reference spur, simultaneously. By removing the power-hungry unit-gain amplifier and reducing the turn-on time of the reference current sources, the current mismatch and power efficiency are both optimized by only one rail-to-rail single-stage amplifier. Fabricated in 65-nm CMOS process, the proposed DPPLL is verified, and it achieves −122-dBc/Hz@1MHz phase noise and −66.3-dBc reference spur at 4.4-GHz output. The integrated jitter is 89.7 fs from 10 kHz to 100 MHz with a total power consumption of 10.4 mW at 1.2-V supply, and a −250.8-dB figure of merit (FOM) is achieved.