학술논문

A fine-grain parallel architecture based on barrier synchronization
Document Type
Conference
Source
Proceedings of the 1996 ICPP Workshop on Challenges for Parallel Processing Parallel processing Parallel Processing, 1996. Vol.3. Software., Proceedings of the 1996 International Conference on. 1:247-250 vol.1 1996
Subject
Computing and Processing
Communication, Networking and Broadcast Technologies
Parallel architectures
Delay
Prototypes
Processor scheduling
Hardware
Computer architecture
Sampling methods
Concurrent computing
Workstations
Control systems
Language
ISSN
0190-3918
Abstract
Although barrier synchronization has long been considered a useful construct for parallel programming, it has generally been either layered on top of a communication system or used as a completely independent mechanism. Instead, we propose that all communication be made a side-effect of barrier synchronization. This is done by extending the barrier synchronization unit to collect a datum from each processor, compute an aggregate function, and return the corresponding result to each processor. This paper describes a scalable prototype implementation of PAPERS (Purdue's Adapter for Parallel Execution and Rapid Synchronization). Despite the fact that the prototype is implemented as very simple TTL hardware connecting conventional workstations, measured performance on fine-grain parallel communication operations is far superior to that obtained using conventional workstation networks. It is comparable to the performance of commercially available supercomputers.