학술논문
MOSFET matching improvement in 65nm technology providing gain on both analog and SRAM performances
Document Type
Conference
Author
Source
Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005. Microelectronic Test Structures Microelectronic Test Structures, 2005. ICMTS 2005. Proceedings of the 2005 International Conference on. :137-142 2005
Subject
Language
ISSN
1071-9032
2158-1029
2158-1029
Abstract
The 65 nm process has been optimized through thermal budget and implant of halo and LDD to reduce gate impact. It provides the best matching results ever reported to our knowledge, i.e. A/sub Vt/ of 2.1 and 1.9 mV./spl mu/m for NMOS and PMOS respectively. We demonstrate that such results provide relevant circuit performance improvement. For SRAM, a gain of more than 50% has been achieved on cell read current going from 4 down to 2.1 mV./spl mu/m. For analog applications, significant improvement is pointed out in terms of linearity and resolution.