학술논문
200 mm process integration for a 0.15 /spl mu/m channel-length CMOS technology using mixed X-ray/optical lithography
Document Type
Conference
Author
Source
Proceedings of 1994 IEEE International Electron Devices Meeting Electron devices Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International. :695-698 1994
Subject
Language
ISSN
0163-1918
Abstract
An integrated 0.35 /spl mu/m CMOS technology with 0.15 /spl mu/m effective channel length (L/sub EFF/) is demonstrated in a 200 mm line. X-ray lithography is used for the critical gate level, along with conventional deep-UV and mid-UV lithography for other levels. Shallow Trench Isolation (STI) is used to achieve 0.35 /spl mu/m design rules. The NFET and PFET devices are designed for operation with a scaled power supply of 1.8 V. This technology provides 50% performance improvement relative to a 2.5 V, 0.5 /spl mu/m design rule, 0.25 /spl mu/m L/sub EFF/ high-performance CMOS technology.ETX