학술논문
Subthreshold capable, asynchronous FPGA in a 14nm SOI process
Document Type
Conference
Author
Source
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE. :1-2 Oct, 2015
Subject
Language
Abstract
We have designed a subthreshold-enabled FPGA (seFPGA) that has been sent for fabrication. The seFPGA has a general purpose, but asynchronous architecture that contains 50,880 16-bit LUTs with 4 voltage domains. Furthermore, the architecture is appropriate for the floating-gate or SRAM state storage.