학술논문

Device level 3-dimensional ICs: Membrane projection lithography for advanced manufacturing
Document Type
Conference
Source
2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Electron Devices and Solid-State Circuits (EDSSC), 2015 IEEE International Conference on. :379-382 Jun, 2015
Subject
Components, Circuits, Devices and Systems
Fabrication
Silicon
Lithography
Integrated circuits
Etching
Implants
Standards
3DIC
fabrication
advanced interconnects
Language
Abstract
Membrane projection lithography (MPL) is proposed as a method for creation of 3-dimensional integrated circuits at the device level as opposed to stacking 2-D die. In MPL, standard semiconductor fabrication processes and equipment are used in a novel sequence of processing steps to create 3 dimensional micrometer-scale structures. Generalization of MPL from strictly deposition to ion implantation and dry etching, combined with blanket processes such as CVD deposition and oxidation, provide all the necessary ingredients for fabrication of integrated circuit devices in all three coordinate axes in high topography silicon.