학술논문
11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip
Document Type
Conference
Author
Cassidy, Andrew S.; Arthur, John V.; Akopyan, Filipp; Andreopoulos, Alexander; Appuswamy, Rathinakumar; Datta, Pallab; Debole, Michael V.; Esser, Steven K.; Otero, Carlos Ortega; Sawada, Jun; Taba, Brian; Amir, Arnon; Bablani, Deepika; Carlson, Peter J.; Flickner, Myron D.; Gandhasri, Rajamohan; Garreau, Guillaume J.; Ito, Megumi; Klamo, Jennifer L.; Kusnitz, Jeffrey A.; McClatchey, Nathaniel J.; McKinstry, Jeffrey L.; Nakamura, Yutaka; Nayak, Tapan K.; Risk, William P.; Schleupen, Kai; Shaw, Ben; Sivagnaname, Jay; Smith, Daniel F.; Terrizzano, Ignacio; Ueda, Takanori; Modha, Dharmendra
Source
2024 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2024 IEEE International. 67:214-215 Feb, 2024
Subject
Language
ISSN
2376-8606
Abstract
The Deep Neural Network (DNN) era was ushered in by the triad of algorithms, big data, and more powerful hardware processors for training large-scale neural networks. Now, the ubiquitous deployment of DNNs for neural inference in edge, embedded, and data center applications demands more power-efficient hardware processors, while attaining increasingly higher computational performance. To address this Inference Challenge, we developed the NorthPole Architecture and implemented a NorthPole Chip instantiation [1, 2].