학술논문
Design and implementation of a scalable multimedia processor
Document Type
Conference
Author
Source
IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings. SOC conference SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]. :89-92 2003
Subject
Language
Abstract
This work describes the design and implementation of a highly customisable multimedia processor. The proposed core has been developed with the goal of simplicity and effectiveness. Moreover, thanks to its soft-core nature, it is suited for being implemented over different physical layers. In particular, in this paper, an FPGA-oriented implementation is addressed. Additionally, this core can be configured to contain a different number of functional units depending on the specific application. In order to validate the proposed approach, three different configuration profiles have been fully implemented on a Xilinx Virtex XCV2000E FPGA.