학술논문

Low level segmentation using CMOS smart hexagonal image sensor
Document Type
Conference
Source
Proceedings of Conference on Computer Architectures for Machine Perception Computer architectures for machine perception Computer Architectures for Machine Perception, 1995. Proceedings. CAMP '95. :21-28 1995
Subject
Computing and Processing
Signal Processing and Analysis
Image segmentation
CMOS image sensors
Image sensors
Very large scale integration
Intelligent sensors
Computer architecture
Spatial resolution
Analog computers
Computer vision
CMOS technology
Language
Abstract
The exploitation of analog VLSI techniques combined with computer vision knowledge offers spectacular possibilities. Limitations of current VLSI technologies do not allow to create sensors with extremely complex pixel architecture, but the coupling of external CMOS analog processing units is a great solution for rapid low level segmentation processes. This paper presents a novel sensing approach where photo-transduction, multiresolution feature extraction, scale-space integration, and edge tracking combined with sub-pixel interpolation are performed on a mixed-signal (digital-analog) VLSI architecture. The paper also discusses how we implement the curvature primal sketch into the system for higher level scene representation. The main sensory part of this integrated image acquisition system is a CMOS sensor called Multiport Access photo-Receptor (MAR). VLSI also provides means to integrate analog computing, digital controller, and DSP co-processor modules which define a powerful sensory chip set for focal plane image processing. A current version of the MAR sensor which implements 256/spl times/256 pixels includes 16 analog spatial filters which simultaneously compute multiresolution edge maps. This novel smart image sensor approach with associated low level segmentation capability presents good opportunities for real time automated process for the particular case of unstructured environment.