학술논문
A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET
Document Type
Conference
Author
Vaz, Bruno; Verbruggen, Bob; Erdmann, Christophe; Collins, Diarmuid; Mcgrath, John; Boumaalif, Ali; Cullen, Edward; Walsh, Darragh; Morgado, Alonso; Mesadri, Conrado; Long, Brian; Pathepuram, Rajitha; De La Torre, Ronnie; Manlapat, Alvin; Karyotis, Georgios; Tsaliagos, Dimitris; Lynch, Patrick; Lim, Peng; Breathnach, Daire; Farley, Brendan
Source
2018 IEEE Symposium on VLSI Circuits VLSI Circuits, 2018 IEEE Symposium on. :99-100 Jun, 2018
Subject
Language
Abstract
A 13bit 5GS/s time-interleaved ADC is described which uses a chopping technique to reduce the effect of interleaved flicker noise spectral artefacts and to increase the ADC immunity to input signal characteristics. Enhanced offset and time-skew calibration algorithms are developed to maximize the performance in the presence of non-ideal sampling switches. At 5GS/s, the ADC dissipates 641mW while achieving a 62dB and 57dB of SFDR and SNDR respectively while maintaining a SFDR excluding HD2 and HD3 better than 70dBc across the first Nyquist band for input amplitudes down to −20dBFS.