학술논문

Efficient Spatial Processing Element Control via Triggered Instructions
Document Type
Periodical
Source
IEEE Micro Micro, IEEE. 34(3):120-137 Jun, 2014
Subject
Computing and Processing
Instruction sets
Programming
Field programmable gate arrays
Computer architecture
Hardware
Parallel processing
Radiation detectors
networking
triggered instruction
processing element
spatial parallelism
hardware
high performance computing
Language
ISSN
0272-1732
1937-4143
Abstract
In this article, the authors present triggered instructions, a novel control paradigm for arrays of processing elements (PEs) aimed at exploiting spatial parallelism. Triggered instructions completely eliminate the program counter and allow programs to transition concisely between states without explicit branch instructions. They also allow efficient reactivity to inter-PE communication traffic. The approach provides a unified mechanism to avoid overserialized execution, essentially achieving the effect of techniques such as dynamic instruction reordering and multithreading, which each require distinct hardware mechanisms in a traditional sequential architecture.