부산대학교 도서관

This paper presents a cost-effective method using 3D printing technology to reduce the parasitic losses when probing a channel with a logic analyzer compared to traditional methods. The method is demonstrated on a 16 Gb/s PCIe Gen4 channel, taking advantage of the physically accessible SMT AC decoupling capacitors through a custom fixture to contact the signals of the high-speed serial (HSS) channel.Channel topology, length and transceiver compensation, and sophisticated equalization has increased link frequency dramatically at the cost of complexity. This renders traditional debug activities using an oscilloscope to be of very limited value in the characterization and verification of the link. The protocol-awareness of HSS links, including the use of retimers, makes the use of a logic analyzer necessary.While a logic analyzer fills the need for protocol analysis and timing data to debug link errors that would be undetected by traditional oscilloscope efforts, the fixturing to contact the signals introduces an electrical loading in the channel. As data rates continue to increase, the loading becomes increasingly severe. The commonly available probe connectors for logic analyzers are physically large, require substantial board real estate, and consume a notable percentage of channel margin due to its parasitic losses.With the proposed method, HSS channels can be analyzed during link operation and link training. Prototype parts can be analyzed and, with fore-thought and planning, even failure analysis of customer-failing parts can be investigated. The fixturing is affordable, compact, and configurable using 3D printing technology promising continued use as HSS data rates continue to increase.