학술논문

Multiplication by complements
Document Type
Conference
Source
CONIELECOMP 2012, 22nd International Conference on Electrical Communications and Computers Electrical Communications and Computers (CONIELECOMP), 2012 22nd International Conference on. :153-156 Feb, 2012
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Fields, Waves and Electromagnetics
Computing and Processing
Hardware
Delay
Algorithm design and analysis
Arrays
Adders
Organizations
Language
Abstract
An innovative multiplication method is proposed which solves the problem of finding the product of two unsigned binary numbers by forming successively smaller one's complements of the operands. The foundation of the algorithm lies in an ancient Vedic algorithm for multiplication. The Vedic multiplication algorithm is adapted to operate on binary numbers. The correctness of the method is demonstrated formally and translated into hardware. The resulting n-bit multiplier architecture consists of n-stages, each stage reducing the size of the operands by 1-bit.