부산대학교 도서관

Decimal arithmetic is gaining prominence in many commercial applications where a high degree of accuracy is desired. Some of these include currency conversion and internet based financial transactions. This paper explores various weighted Binary Coded Decimal (BCD) coding schemes to find one efficient representation that can be used to design a hardware and delay efficient BCD adder. Out of the wide range of possibilities, some representations are more desirable than the others because of certain inherent properties they possess. This paper summarizes the properties that make a particular BCD representation more attractive than others to implement a decimal adder. It is found that one of the 4221 encoding schemes possesses most of these properties. Finally, it also provides the design and implementation of a multi-digit decimal adder using the best coding scheme. The implementation is on a Spartan 3E FPGA chip. The proposed design is compared with an excess-three adder which is one of the fastest adders using alternative coding methods.