학술논문
Evaluation of test strategies for multichip modules
Document Type
Conference
Author
Source
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International. :234-237 1992
Subject
Language
Abstract
Two parallel testing strategies for multichip modules-the boundary-scan technique and the cascadable built-in tester (CBIT)-are evaluated in terms of testing time, fault coverage, and area overhead. Results on a small-scale processor configuration favor the CBIT design for test effectiveness of the chip, and the boundary-scan design for area overhead interconnection tests.ETX