학술논문

A new approach using symbolic analysis to compute path-dependent effective properties preserving hierarchy
Document Type
Conference
Source
2014 27th IEEE International System-on-Chip Conference (SOCC) System-on-Chip Conference (SOCC), 2014 27th IEEE International. :404-408 Sep, 2014
Subject
Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Signal Processing and Analysis
Resistance
Resistors
System-on-chip
Logic gates
Performance evaluation
Algorithm design and analysis
Electrostatic discharges
Electrostatic Discharge (ESD)
Electrical Overstress (EOS)
System-On-Chip (SOC)
Layout-vs-Schematic (LVS)
Electronic Design Automation (EDA)
Design Rule Checks (DRC)
Electrical Rule Checks (ERC)
Intellectual Property(IP)
Hard IP (HIP)
Language
ISSN
2164-1676
2164-1706
Abstract
This paper describes a technique to calculate an effective property of intentional devices, like resistors, preserving design hierarchy. Traditional methods of computing effective properties like point-to-point resistance, involved using a flat netlist and solving a conductance matrix or flattening a hierarchical netlist and applying reduction techniques to reduce parallel and series resistors. These traditional techniques are not conducive to computing effective resistances on partial paths in hierarchical designs and then using those values to do other rule checks. This is because flattening a netlist of millions of devices to compute a partial path property is very expensive in memory. This paper focuses on an algorithm to efficiently compute effective path-dependent properties on intentional devices in a netlist.