부산대학교 도서관

This letter presents a 56-Gb/s PAM-4 transceiver which achieves a bit error rate of $2\times 10^{-9}$ through −33 dB of channel insertion loss while consuming 500-mW receiver and 90-mW transmitter power. Its compact 0.31-mm 2 area is achieved by rigorously applying a digital design style to exploit the high logic density offered by the 7-nm technology node. This is realized by an all-digital PLL, source-series-terminated transmitter, and synthesized DSP section for the majority of the receiver signal processing. Receiver analog signal conditioning is limited to 8-dB of peaking provided by a low-distortion analog frontend that feeds a 28-GS/s 8-bit ADC implemented as an 8-way time-interleaved SAR-ADC array. Digital receiver signal equalization, as well as timing recovery, relies on adaptive filtering which eliminates the need for training sequences, a concept extended to ADC calibration. Here, signal distortion caused by sampling clock skew and SAR-ADC array mismatch is removed by fully adaptive feedback loops.