부산대학교 도서관

The design details of K band 6 bit digital phase shifter circuit in 65nm CMOS technology (MMIC) for phased array antennae in general and active phased array antennae in particular, are presented in this paper. The circuit is composed of Si CMOS switches and filter based phase shifting network. The 6 bits are designed individually using the lumped equivalents and then connected together. The switches form an integral part of the design. The parasitic impedances associated with the switches are compensated in the design. With 6 bits, a total of 64 states are derived with different switching combination, and coverage of 360 is achieved. The insertion loss is observed to be $-13\pm 6.5$ dB and the input and output matching was greater than 5 dB over the band of 19–20 GHz. The RMS phase error achieved is 3° at the centre frequency of 20 GHz. The area of the design is $1.255\ \text{mm}\times 0.424\ \text{mm}$, the circuit operates at 1.2V and the power consumed is almost low.