학술논문

Generation of an ordered sequence of test vectors for single state transition faults in large sequential machines
Document Type
Conference
Source
Proceedings 10th Asian Test Symposium Asian test symposium Test Symposium, 2001. Proceedings. 10th Asian. :279-284 2001
Subject
Components, Circuits, Devices and Systems
Signal Processing and Analysis
Power, Energy and Industry Applications
Circuit testing
Circuit faults
Sequential analysis
Fault detection
Electrical fault detection
Sequential circuits
Computer science
Tires
Language
ISSN
1081-7735
Abstract
A new strategy for the generation of test vectors for testing large sequential machine has been proposed. The fault model assumed is the single state transition (SST) fault model where a fault corrupts the destination state of exactly one transition of the machine, the rest of the transitions being unaffected. The strategy takes into consideration the behaviour of the machine under test and generates a set of test vectors. The main contribution of this paper is that it creates an ordering of the test vectors generated, if these test vectors are applied in the same order during testing, it maximizes the fault coverage in the least possible time with high probability. Also this approach reduces the traversal space of the machine under test by eliminating a set of transitions where the chance of detecting an existing fault is poor. The approach also ensures that the test vectors are such that when applied for testing they do not result in the repeated traversal of the same part of the machine. This helps in reducing the time of testing without compromising the extent of fault coverage of the testing procedure.