부산대학교 도서관

Advances in the high performance computing (HPC) lead to a new frontier of the fan out wafer level packaging (FOWLP) development. To provide a solution of cost-attractive package for heterogeneous chip integration, FOWLP has recently emerged as an indispensable platform. Herein, we propose novel 2.5D re-distribution layer (RDL) interposer packaging technology including the fabrication of fine-pitch RDL interposer (>560 mm 2 ) assembled with one high-bandwidth memory (HBM) and two ASICs, in order to achieve the TSV-less and cost-effective package. The intrinsic features of the fine-pitch RDL interposer enhances the integrity of the signals and the reliability of the bump joints, and thus integrates multiple chips and accommodates higher I/O counts. With the fine-pitch 2.5D RDL interposer technology, the system-in-package is fabricated in order to substantiate the functions of the HBM, and tested to analyze the characteristics of its performance. The fine-pitch 2.5D RDL interposer package demonstrates up to 3.2Gbps/pin operation with the HBM, and also shows excellent reliability without any failure during the reliability tests (TC1000hr, b-HAST 264hr, u-HAST 264hr and HTS1000hr). The proposed 2.5D RDL interposer technology can be a promising solution for the cost-effective and large size 2.5D packaging in the HPC applications.