학술논문
A 5 dBm 30.6% Efficiency 915 MHz Transmitter with $210\ \mu \mathrm{W}$ ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer
Document Type
Conference
Author
Source
2020 IEEE Asian Solid-State Circuits Conference (A-SSCC) Solid-State Circuits Conference (A-SSCC), 2020 IEEE Asian. :1-4 Nov, 2020
Subject
Language
Abstract
This paper presents a 915 MHz binary frequency-shift keying (BFSK) internet of things (IoT) transmitter (TX) utilizing a frequency tripler driven by duty and phase calibrated signal. The proposed frequency tripling method is adopted to suppress the unwanted harmonic spurs generated from the conventional frequency tripler followed by a class-D power amplifier (PA), relaxing the requirement for the harmonic filtering at the PA output. Implemented in a 55 nm CMOS, the proposed TX achieves the output power of 5 dBm and efficiency of 30.6% with an on-chip PA matching network (MN) while dissipating a dc power of $210\ \mu \mathrm{W}$ in the synthesizer.