학술논문
How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology
Document Type
Conference
Author
Chiang, H.-L.; Hadi, R. A.; Wang, J.-F.; Han, H.-C.; Wu, J.-J.; Hsieh, H.-H.; Horng, J.-J.; Chou, W.-S.; Lien, B.-S.; Chang, C.-H.; Chen, Y.-C.; Wang, Y.-H.; Chen, T.-C.; Liu, J.-C.; Liu, Y.-C.; Chiang, M.-H.; Kao, K.-H.; Pulicherla, B.; Cai, J.; Chang, C.-S.; Su, K.-W.; Cheng, K.-L.; Yeh, T.-J.; Peng, Y.-C.; Enz, C.; Chang, M.-C. F.; Chang, M.-F.; Wong, H.-S. P.; Radu, I. P.
Source
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2023 IEEE Symposium on. :1-2 Jun, 2023
Subject
Language
ISSN
2158-9682
Abstract
Given the limited space and cooling capacity in dilution refrigerators, it is challenging to scale the number of qubits for a fault-tolerant quantum computer (QC). In this paper, we study a custom-scaled CMOS technology to overcome the constraints in the dilution refrigerators. With Cryo-Design/ Technology CoOptimization (Cryo-DTCO) in an advanced node, one can then reduce the control power from 26.8 mW/ qubit to 8.4 mW/ qubit $(\sim 0.31 \times)$. Projections suggest this may be sufficient to enable error corrections via surface codes for fault-tolerant computing.