학술논문
MLC PCM Techniques to Improve Nerual Network Inference Retention Time by 105X and Reduce Accuracy Degradation by 10.8X
Document Type
Conference
Author
Source
2021 Symposium on VLSI Technology VLSI Technology, 2021 Symposium on. :1-2 Jun, 2021
Subject
Language
ISSN
2158-9682
Abstract
We present three novel MLC PCM techniques – (1) device requirement balancing, (2) prediction-based MSB-biased referencing, and (3) bit-prioritized placement to address the MLC device challenges in neural network applications. Using measured MLC bit error rates, the proposed techniques can improve the MLC PCM retention time by 10 5 times while keeping the ResNet-20 inference accuracy degradation within 3% and reduce the accuracy degradation by 91% (10.8X) for CIFAR-100 dataset in the presence of temporal resistance drift.