학술논문
A high-voltage p-LDMOS with enhanced current capability comparable to double RESURF n-LDMOS
Document Type
Conference
Author
Source
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Power Semiconductor Devices and ICs (ISPSD), 2018 IEEE 30th International Symposium on. :148-151 May, 2018
Subject
Language
ISSN
1946-0201
Abstract
In this paper, a simple p-LDMOS structure with significantly improved performances based on a novel three dimensional concept is proposed. The hole current in the Ptop region of the signal region flows into the floating P + , then through the integrated resistor R p formed by the Pbase region in the z-axis direction with a distance of W 2 +W 3 , into electrode D. A voltage drop (V Gn ) which controls the n-channel will be auto-generated across R p during the on- and off-state of the hole current. Thus the p-LDMOS applies both hole and electron as majority carriers to conduct current. The proposed p-LDMOS, having only one external controlling signal (G P ), has a current capability comparable to or even larger than that of an optimized double RESURF n-LDMOS implemented through the same process steps. The power loss can be reduced by 74.9% compared with the conventional p-LDMOS.