부산대학교 도서관

This paper describes an ATE extension module that enables a low-cost test system to be applied to advanced (multi-GHz) memories. The target application is for testing memories with data rates above 3.2Gbps. The test module uses state-of-the-art FPGAs for economical autonomous pattern synthesis and comparison under the high-level supervision of a low-cost “host” test platform (ATE). The FPGA logic capabilities are complemented by custom 4-channel “pin electronics” (PE) modules with I/O performance comparable to advanced ATE. The PE modules provide input/output/bidirectional signal conditioning, including amplitude, format, timing, and pre-emphasis, and a “shadow sampler.”