부산대학교 도서관

As ever-increasing bandwidth demand pushes wireline transceiver data-rates beyond 25Gb/s, the clocking solution for multi-protocol support over a wide range of data-rates becomes a key design challenge. In [1], an injection-locked multi-phase clock generator demonstrated wideband operation and a high-resolution phase rotator using CML in 28nm FDSOI CMOS. However, in 7nm FinFET technology, the CML implementation suffers from the reduced supply level and output impedance degradation at high temperatures. In order to scale power consumption with data-rate, CML implementation also needs to employ bias current and load programmability, further impacting its performance. For these reasons, the supply-regulated inverter-based clocking scheme is proposed. Furthermore, the full inverter-based clock chain generates smaller random jitter (RJ) because of the faster edge-rate compared to a CML implementation. Supply regulation, applied as part of the calibration loop, mitigates the sensitivity to inverter delay and edge-rate over the process and temperature variations. This design, benefiting from its mostly-digital structure, adopts “sea of gates” layout style with optimized via patterns and uniform metal tracks, which effectively alleviate the significant parasitic resistance variations on low level metals fabricated by multiple patterning in 7nm FinFET.