학술논문
An optoelectronic CMOS circuit implementing a simulated annealing algorithm
Document Type
Periodical
Author
Source
IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 31(7):1046-1050 Jul, 1996
Subject
Language
ISSN
0018-9200
1558-173X
1558-173X
Abstract
An original optoelectronic implementation of simulated annealing is presented. A compact and simple optical system provides a chip with arrays of independent random noise sources. The silicon chip is composed of a mesh of computing cells. Each cell includes both analog and digital circuits and includes two photosensors. A detailed analysis of this cell is given including a presentation of the design constraints. A 4/spl times/4-cells prototype chip was implemented in a 1 /spl mu/m CMOS digital technology and was successfully operated at 20000 iterations per second. The measurements and characterization of this chip made possible the successful design of a 600-cells chip also presented. These results demonstrate the video-rate application of simulated annealing to early vision tasks.