학술논문

Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond
Document Type
Conference
Source
2020 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2020 IEEE International. :20.3.1-20.3.4 Dec, 2020
Subject
Components, Circuits, Devices and Systems
Silicon compounds
Resistance
Annealing
Tin
Business process re-engineering
Electrical resistance measurement
Plugs
Language
ISSN
2156-017X
Abstract
This paper reports BPR/Via-to-BPR (VBPR) module development at 24nm fin pitch (FP) / 42nm contacted gate pitch (CPP), and W and Ru-BPR and Ru- Contact-to-Active (M0A)/VBPR resistance (R) & electromigration (EM). BPR dielectric barrier, BPR plug barrier, and fin reveal are optimized to enable BPR scaling. A self-aligned VBPR etch is also demonstrated by Q-ALE process. Ru-BPR meets BPR line R target < 50 Ω/μm at ~2x smaller aspect ratio than W-BPR thanks to its lower resistivity and thinner TiN liner. A good VBPR pre-clean prior to TiN liner & Ru deposition with W-BPR underneath, is found to be crucial to achieve low Ru-VBPR resistance. Calibrated TCAD simulations show Ru-VBPR with thin TiN liner meets VBPR R target < 75 Ω. W-BPR interface with Ru-VBPR shows robust electromigration for >1100 h at 5 MA/cm 2 at 330 °C.