부산대학교 도서관

This article presents a compact analog-to-digital converter (ADC)/digital-to-analog converter (DAC) digital signal processing (DSP)-based long reach (LR) transceiver in 7-nm FinFET technology that operates seamlessly from 3.5—56 Gb/s in pulse-amplitude modulation (PAM-4) [from 1.25 to 28 Gb/s in non-return to zero (NRZ) mode] and consumes only 243 mW at 56 Gb/s. The receiver (RX) front end consists of a two-stage continuous-time linear equalizer (CTLE), a 40-way time-interleaved (TI) successive approximation register (SAR)-ADC, a DSP equalizer containing a 17-tap feed-forward equalizer (FFE) working concurrently with a one-tap speculative decision feedback equalizer (DFE) and a reflection canceling FFE, which implements four individually roaming taps. Clock recovery is achieved on a dedicated low latency path consisting of a five-tap FFE, slicer, time error detector (TED), and loop filter driving a dedicated LC —digital-controlled oscillator (DCO). The transmit section consists of a variety of pattern generators, a five-tap finite impulse response (FIR) section, and a terminated DAC as an analog transmitter. When working on a 42.5-dB-LR channel at 56 Gb/s PAM-4, the transceiver consumes 243 mW from the 0.9-V (analog) and 0.75-V (digital) supplies, corresponding to an efficiency of 4.3 pJ/b.