학술논문
An 80MHz 4/spl times/ oversampled cascaded /spl Delta//spl Sigma/-pipelined ADC with 75dB DR and 87dB SFDR
Document Type
Conference
Author
Source
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005. Solid-State Circuits Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International. :174-591 Vol. 1 2005
Subject
Language
ISSN
0193-6530
2376-8606
2376-8606
Abstract
A 2/sup nd/-order 4b /spl Delta//spl Sigma/ modulator in cascade with a 9b pipeline clocked at 80MHz achieves 75dB DR, 74dB peak SNR and more than 87dB SFDR in a 10MHz bandwidth by means of background digital linearization and noise-cancellation algorithms. The 0.18/spl mu/m CMOS chip consumes 240mW including reference generator, digital decimator and correction logic.