학술논문

Accelerating Chip Design With Machine Learning
Document Type
Periodical
Source
IEEE Micro Micro, IEEE. 40(6):23-32 Jan, 2020
Subject
Computing and Processing
Chip scale packaging
Computational modeling
Task analysis
Logic gates
Training
Very large scale integration
Data models
Design Methodology
Integrated Circuits
Machine Learning
VLSI
Language
ISSN
0272-1732
1937-4143
Abstract
Recent advancements in machine learning provide an opportunity to transform chip design workflows. We review recent research applying techniques such as deep convolutional neural networks and graph-based neural networks in the areas of automatic design space exploration, power analysis, VLSI physical design, and analog design. We also present a future vision of an AI-assisted automated chip design workflow to aid designer productivity and automate optimization tasks.