학술논문

Peak-SNR Analysis of CMOS TDCs for SPAD-Based TCSPC 3D Imaging Applications
Document Type
Periodical
Source
IEEE Transactions on Circuits and Systems II: Express Briefs IEEE Trans. Circuits Syst. II Circuits and Systems II: Express Briefs, IEEE Transactions on. 68(3):893-897 Mar, 2021
Subject
Components, Circuits, Devices and Systems
Jitter
Phase noise
Ring oscillators
Photonics
Three-dimensional displays
Imaging
Time-correlated single-photon counting (TCSPC)
LiDAR
single-photon avalanche diode (SPAD)
time-to-digital converter (TDC)
time-of-flight (TOF)
ring oscillator
frequency divider
jitter
SNR
CMOS
figure-of-merit
Language
ISSN
1549-7747
1558-3791
Abstract
TDCs formed by ring oscillators are arrayable, scalable, and low power, making them suitable for SPAD-based TCSPC 3D imaging systems. The TDC precision affects the ranging accuracy and, hence, the quality of the reconstructed 3D image. This brief studies the jitter of ring-oscillator-based TDCs as a function of their full-scale-range and derives an expression for the TDC total jitter. The introduced behavioral model describes three different regions of the SNR for TDCs. A peak- SNR design-point is identified. Increasing the full-scale-range of the TDC beyond this point entails increased jitter and, thus, ultimately a declining SNR . The analysis is validated using post-layout simulations of a ring-oscillator-based TDC designed in 65nm CMOS. A TDC resolution degradation factor defines the TDC jitter behavioral model. It is consistent with FOMs that have been used in the past to evaluate TDCs and clarifies their underlying assumptions.