학술논문
A 112–134-Gb/s PAM4 Receiver Using a 36-Way Dual-Comparator TI-SAR ADC in 7-nm FinFET
Document Type
Periodical
Author
Source
IEEE Solid-State Circuits Letters IEEE Solid-State Circuits Lett. Solid-State Circuits Letters, IEEE. 3:138-141 2020
Subject
Language
ISSN
2573-9603
Abstract
This letter describes a 112–134-Gb/s PAM-4 wireline receiver (Rx) designed and fabricated in 7-nm CMOS FinFET technology. The Rx includes a T-Coil-assisted on-die termination (ODT), an adaptable continuous-time linear equalizer (ACTLE), a time-interleaved ADC (TI-ADC), clock generation, clock distribution, feed-forward equalizer (FFE), decision feedback equalizer (DFE), and calibration. The TI-ADC is implemented as a 56–67-GSa/s, 36-way arrangement of dual-comparator SAR ADCs (SAR subADCs). The Rx achieves BER better than 1e-4 for a data rate as high as 127 Gb/s, with 3.2e-4 BER at 134.4 Gb/s, over a 15-dB die-to-die loss channel and achieves 3e-6 BER over a 33-dB die-to-die channel loss at 28-GHz Nyquist while consuming 5.1 pJ/b of power, excluding DSP power.