학술논문

Partitioning conditional data flow graphs for embedded system design
Document Type
Conference
Source
Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors Application specific systems, architectures and processors Application-Specific Systems, Architectures, and Processors, 2000. Proceedings. IEEE International Conference on. :339-348 2000
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Flow graphs
Embedded system
Design methodology
3G mobile communication
Energy consumption
Signal processing
GSM
Process design
Space exploration
Reduced instruction set computing
Language
ISSN
2160-0511
Abstract
The complexity of embedded applications increases continuously. Integration advances provides a rising range of possibilities to implement a system on a chip. The designers are faced to the difficult challenge to select the right units to implement the application functionalities so that the silicon area is minimized and the time constraints of the application are met. This paper presents an effective method to design system architectures which operates on a conditional data flow graph which is well suited to represent signal processing applications.