부산대학교 도서관

Because they are capable of generating large output power levels at high efficiencies, Class-D amplifiers are extremely attractive for systems-on-chip in mobile and low-power applications, where battery life and reduced thermal dissipation are crucial parameters. One modification of the general idea of Class-D amplifiers is to drive a power amplifier directly with a digital pulse-width modulated input [1]. This scheme is desirable since it greatly reduces the die area by eliminating high-precision analog circuits such as DACs, pre-amplifiers and programmable precision-gain amplifiers. The elimination of sensitive analog circuits in favor of digital PWM generation is especially more efficient in ultra-deep-submicron (UDSM) processes where analog components are noisier and less precise. The Class-D amplifier system presented in this paper is a second-order architecture that operates on a digital PWM input and eliminates the use of an external carrier signal [2, 3].