학술논문
A 1.5 Ghz VLIW DSP CPU with Integrated Floating Point and Fixed Point Instructions in 40 nm CMOS
Document Type
Conference
Author
Source
2011 IEEE 20th Symposium on Computer Arithmetic Computer Arithmetic (ARITH), 2011 20th IEEE Symposium on. :82-86 Jul, 2011
Subject
Language
ISSN
1063-6889
Abstract
A next generation VLIW DSP Central Processing Unit (CPU) which has an integrated fixed point and floating point Instruction Set Architecture (ISA) is presented. It is designed to meet a 1.5 GHz core clock frequency in a 40nm process with aggressive area and power goals. In this paper, the benchmarking process and benefits of newly defined instructions such as complex matrix multiply is explained. Also, the CPU data path is described in detail, highlighting several novel micro-architecture features. Finally, our design methodology as well as verification methodology to ensure functional correctness utilizing formal equivalent verification is described.