학술논문

Self-Timed Adaptive Digit-Serial Addition
Document Type
Periodical
Source
IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 27(9):2131-2141 Sep, 2019
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Adders
Transistors
Throughput
Delay lines
Latches
Logic gates
Computer architecture
Addition
arithmetic
asynchronous
bundled data (BD)
quasi-delay insensitive (QDI)
Language
ISSN
1063-8210
1557-9999
Abstract
A fundamental operator in modern computational systems has a multitude of highly optimized implementations. In general-purpose systems, the width has grown to 128 bits, putting pressure on designers to use sophisticated carry lookahead or tree adders to maintain throughput while sacrificing area and energy. However, the typical workload mostly exercises the lower 10–15 bits. This leaves many devices on and unused during normal operation, reducing the overall performance. We hypothesize that bit- or digit-serial implementations for arbitrary-length streams represent an opportunity to decrease the overall energy usage while increasing the throughput/area efficiency of the system and verify this hypothesis by constructing an asynchronous digit-serial adder for comparison against its bit-parallel counterparts.