학술논문

System-on-Programmable-Chip AES-GCM implementation for wire-speed cryptography for SAS
Document Type
Conference
Source
2018 Conference on Design of Circuits and Integrated Systems (DCIS) Design of Circuits and Integrated Systems (DCIS), 2018 Conference on. :1-6 Nov, 2018
Subject
Components, Circuits, Devices and Systems
Computing and Processing
IEC Standards
IP networks
Field programmable gate arrays
Encryption
SAS
IEC 61850
IEC 62351
AES-GCM
FPGA
Cryptography
Language
ISSN
2640-5563
Abstract
Communications within modern electric substations are regulated by IEC 61850. This standard lacks security mechanisms that protect the communications, opening the door for possible threads in the form of cyber-attacks. IEC 62351 defines a security extension to protect layer-2 messages with stringent timing requirements. This extension provides data authentication and confidentially making use of an AES-GCM cipher. An extensive analysis of the state of the art in terms of security in the domain of Substation and Automation Systems (SAS) reveals the requirements for implementing the IEC 62351-6. Based on those specifications, a configurable AES-GCM IP core architecture for FPGAs is proposed. After testing the defined IP core, it is compared to academic and commercial alternatives. Results reveal that the proposed solution meets all the requirements to enable an implementation of IEC 62351-6, being a suitable solution for SAS and the most balanced solution in terms of resource usage and performance.