학술논문
A fully integrated dual-mode frequency synthesizer for GSM and Wideband CDMA in 0.5/spl mu/m CMOS
Document Type
Conference
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Source
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Midwest symposium on circuits and systems Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on. 2:866-869 vol.2 2001
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Language
Abstract
A fully integrated dual-mode frequency synthesizer for GSM and Wideband CDMA (WCDMA) is presented. The synthesizer is designed to maximize hardware sharing between the two modes by applying fractional frequency synthesis to GSM mode and integer frequency synthesis to WCDMA mode. The shared components include phase frequency detector (PFD), charge pump (CP), loop filter, integer frequency divider and VCO, which is 70% of the entire synthesizer in term of die area. A high-speed low power dual modulus prescaler is proposed to operate up to 2.1GHz at 3.3V supply voltage with 11.6mW power consumption by simulation. A dual mode VCO is also proposed for the enhanced tuning range with an accumulation mode NMOS varactor for band-to-band tuning and a p/sup +/n junction varactor for in-band tuning. The simulation result shows that the synthesizer phase noise is -112dBc/Hz at 600kHz offset frequency for WCDMA mode and -117 dBc/Hz for GSM mode.