학술논문

Experimental analysis of spiral integrated inductors on low cost integrated circuit processes
Document Type
Conference
Source
Proceedings. IEEE SoutheastCon, 2005. SoutheastCon SoutheastCon, 2005. Proceedings. IEEE. :116-120 2005
Subject
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Fields, Waves and Electromagnetics
Geoscience
Photonics and Electrooptics
Power, Energy and Industry Applications
Spirals
Costs
Q factor
Inductance
CMOS technology
Silicon
Bonding
Active inductors
Radiofrequency integrated circuits
Conductivity
Language
ISSN
1091-0050
1558-058X
Abstract
Integrated spiral inductors are investigated to obtain an optimal design for low cost IC processes. For this study, different inductor structures were fabricated to determine the best topology suited for optimizing the Q factor. The inductor structures studied include patterned ground shield, hollow spiral and stacked inductors. A new design for stacked inductor using two metal layers is developed to reduce the resistive loss of integrated inductors. The hollow spiral inductors and planar spiral inductors have 4.5 turns and 8 turns, respectively. A patterned ground shield is found to enhance the Q factor from 1.9 up to 3.8 in hollow spiral inductors, and from 1.6 up to 2.5 in planar inductors. The new stacked spiral inductors show slightly lower peak inductance values and resonance frequencies. Nevertheless, due to the reduction of resistive loss of inductor traces, the Q factors of the new stacked structure of inductors are improved by about 14%.