학술논문
A Highly Reliable and Cost Effective 16nm Planar NAND Cell Technology
Document Type
Conference
Author
Source
2015 IEEE International Memory Workshop (IMW) Memory Workshop (IMW), 2015 IEEE International. :1-4 May, 2015
Subject
Language
ISSN
2159-483X
2159-4864
2159-4864
Abstract
A 2D 16nm planar NAND cell technology is described with good cell to cell interference and reliability that can be used in a wide variety of applications. This second generation planar cell uses a high-K dielectric stack and a thin poly floating gate to maintain the needed gate coupling ratio and reduce adjacent cell interference. The technology includes select gates with the same planar structure as the cell. This select gate architecture simplifies the manufacturing of this NAND technology.