학술논문
TCAD analysis of FinFET stress engineering for CMOS technology scaling
Document Type
Conference
Author
Source
2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) Simulation of Semiconductor Processes and Devices (SISPAD), 2015 International Conference on. :417-420 Sep, 2015
Subject
Language
ISSN
1946-1569
1946-1577
1946-1577
Abstract
In this paper, we analyze the mechanical stress induced from source/drain embedded SiGe (eSiGe) in multiple generations of FinFET technologies. By leveraging TCAD simulations, we show that high stress over the entire fin height could be achieved with a proper design of the eSiGe cavity. We also find that the stress should not undergo any reduction as the industry continues to scale down CMOS technologies. Hence, it should still play a major role in boosting semiconductor device performance for the next generation of FinFETs.