학술논문
Performance and Variability-Aware SRAM Design for Gate-All-Around Nanosheets and Benchmark with FinFETs at 3nm Technology Node
Document Type
Conference
Author
Source
2022 International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2022 International. :15.1.1-15.1.4 Dec, 2022
Subject
Language
ISSN
2156-017X
Abstract
For the 3 nm technology node, horizontal gate-all-around nanosheet devices offer a non-disruptive process transition from fin technologies with the advantage of full 3D design flexibility and better short-channel control. For SRAM cell design, this enables non-digital n/pFET balancing. In this paper, a performance and variability-aware DTCO flow is used to benchmark nanosheet SRAM cells against fin technologies at 3 nm node, targeted at 45 nm CPP and 21 nm MP. The impact of gate length, fin height, number of nanosheets, effective n/pFET widths, channel doping, and vertical nanosheet pitch is studied. Despite the lower parasitic capacitances of fins, the design freedoms of nanosheets enable superior SRAM operation in terms of both $V_{\min}$ and read delay even at smaller cell areas.