학술논문
A new two-step ΣΔ architecture column-parallel ADC for CMOS image sensor
Document Type
Conference
Source
2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI) Integrated Circuits and Systems Design (SBCCI), 2016 29th Symposium on. :1-6 Aug, 2016
Subject
Language
Abstract
The demand for high resolution CMOS image sensors (CIS) is rising. Analog-to-digital converters (ADC) represent one of the major bottleneck of CIS. One of the candidates to overcome the existing limits is the column-parallel ADC. Column-parallel extended counting ADCs (EC-ADC) are able to reach high resolution thanks to their two-step conversion. However the EC-ADC area increases due to the two-step design. A solution is to use the same hardware twice to perform both steps. This paper proposes a 14-b, 100 kHz Nyquist frequency, two-step incremental ΣΔ (IΣΔ) analog-to-digital converter suitable for column-parallel CIS. Several architectures with different modulator order are compared to determine the most promising one. The proposed architecture, compared to a one-step second order modulator, reduces the total oversampling ratio (OSR) from 150 to 60 to reach a resolution of 14-b. The operational transconductance amplifiers (OTA) is the most critical part in our ADCs. Its required DC-gain is around 80 dB for a 120 MHz gain-bandwidth product (GBW). The ideal DNL and INL of our two-step IΣΔ ADC are respectively +0.55/−0.6 LSB and +0.5/−0.5 LSB. This work achieves a SNDR of 89 dB when a full scale sinusoid of 100 kHz is applied.