학술논문

Power-efficient application-specific VLIW processor for turbo decoding
Document Type
Conference
Source
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) Solid-state circuits conference Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International. :180-181 2001
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
VLIW
Iterative decoding
Processor scheduling
Bit error rate
Application software
Design methodology
Software tools
High level synthesis
Coprocessors
Parallel processing
Language
ISSN
0193-6530
Abstract
A method permits coprocessors to be embedded inside a programmable VLIW processor. Synchronization of the coprocessors and the VLIW processor is determined at compile-time by the VLIW scheduler. The implementation of a power-efficient turbo decoder demonstrates the effectiveness of this method.