부산대학교 도서관

Today’s modern market needs application computational blocks to execute complex operations with an ease to satisfy low power requirements, wherein relentless efforts are being made by the researchers to optimize these computational blocks in terms of speed, power, and area requirements. The core key component in these computational blocks is Multipliers. Since, these multiplier circuits directly effects the performance of overall computation block or overall system, where there is a need to optimize the multiplier circuit. Since, it is already known that the multiplication requires several steps and is a lengthy process, the algorithm of Vedic multiplication is used to speed-up the multiplication process. Moreover, by implementing the Vedic multiplier circuit with the GDI technique, there will be a further reduction in number of transistors and propagation delay. So, here in this paper the Vedic multiplier circuit is implemented by using GDI technique and also 18nm FinFET is deployed for analyzing simulation results. Here, the primary objective is to optimize the proposed multiplier circuitry, where an experimental analysis is conducted by comprising the parameters such as propagation Delay, Power, Area and Power-Delay-Product (PDP). All experimental analysis is done using Cadence Virtuoso.