학술논문
Influence of stress induced CT local layout effect (LLE) on 14nm FinFET
Document Type
Conference
Author
Source
2017 Symposium on VLSI Technology VLSI Technology, 2017 Symposium on. :T228-T229 Jun, 2017
Subject
Language
ISSN
2158-9682
Abstract
In this paper, we present a new local layout effect in 14nm FinFET due to different CT layout designs (CT extension, CT spacing, and PC past RX distance). Based on 14nm FinFET experimental data, the CT LLE effect induces up to 50mV Vtsat shift, and ∼20% current change. NFET performance is enhanced by ∼7%, while the PFET performance shows slight degradation. Based on TCAD simulation, the CT LLE is fully analyzed and explained by the tensile stress induced in the inter-layer dielectric (ILD).