부산대학교 도서관

Intrinsic tunneling and leaky paths due to neutral trapping centers created by plasma exposure are two key leakage mechanisms in MOS devices with ultrathin oxide. Recently, a third kind of leakage has been identified. It occurs during sweeps of the gate voltage using a stepped ramp in the pre-Fowler-Nordheim (FN) tunneling range (Fonash et al., 1996; Okandan et al., 1997; Balasinski et al., 1997). Unlike the two other mechanisms, the trap-assisted leakage, which has been attributed to charge trapping and carrier recombination in the depletion region, is transient in character and is less dependent on gate oxide thickness. A simple technique to investigate transient current (TC) was proposed by Fonash et al. (J. Appl. Phys. vol. 79, no. 4, p. 2091, 1996). TC can provide insight into some features of plasma-induced damage, such as the spatial distribution, which may not be studied using, for example, capacitance-voltage (C-V) techniques. However, its correlation to Si-SiO/sub 2/ interface quality, device structure, and process parameters have not been covered in the literature. This work demonstrates the application of transient current characteristics to plasma-induced damage analysis and its dependence on the type of the structure. A correlation to C-V-based interface trap data shows that the leakage current is correlated to both Si-SiO/sub 2/ interface quality and defects at isolation edges. Our data shows that the TC technique is simple, straightforward, and sensitive, and could be successfully applied for evaluation of plasma damage.