부산대학교 도서관

An ultra-low-power logarithmic amplifier is presented in order to use in the front-end of preconditioning stages of bio-potential and neural recording microsystems. In such applications, low-power and low-noise performance is very challenging and important. The proposed true logarithmic amplifier, designed by making use of the piece-wise linear approximation and based on the parallel summation topology, includes five low-power limiting amplifiers. In this amplifier, the DC offset removal mechanism applies a low-pass filter in the feedback loop to reject the input offset. This amplifier has been simulated in a 0.18 μm CMOS technology. The simulation results demonstrate a CMRR of 134.7 dB at 50/60 Hz and an input referred noise of 2.53 μV rms in a bandwidth of 0.1–10 kHz. To reduce the power consumption, all transistors are biased in sub-threshold region. The power consumption is 3.72 μW from a 1.2 V power supply.